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| MC14106B Hex Schmitt Trigger The MC14106B hex Schmitt Trigger is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. These devices find primary use where low power dissipation and/or high noise immunity is desired. The MC14106B may be used in place of the MC14069UB hex inverter for enhanced noise immunity or to "square up" slowly changing waveforms. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. Features http://onsemi.com MARKING DIAGRAMS 14 MC14106BCP AWLYYWWG PDIP-14 P SUFFIX CASE 646 1 14 14106BG AWLYWW SOIC-14 D SUFFIX CASE 751A 1 * Increased Hysteresis Voltage Over the MC14584B * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-power TTL Loads or One Low-power * * * Schottky TTL Load Over the Rated Temperature Range Pin-for-Pin Replacement for CD40106B and MM74C14 Can Be Used to Replace the MC14584B or MC14069UB Pb-Free Packages are Available 14 14 1 14 106B ALYWG G 1 MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C TSSOP-14 DT SUFFIX CASE 948G A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/C From 65C To 125C (c) Semiconductor Components Industries, LLC, 2006 October, 2006 - Rev. 7 1 Publication Order Number: MC14106B/D MC14106B 1 3 5 9 11 13 VDD = PIN 14 VSS = PIN 7 2 4 6 8 10 12 Figure 1. Logic Diagram Figure 2. Equivalent Circuit Schematic (1/6 of Circuit Shown) ORDERING INFORMATION Device MC14106BCP MC14106BCPG MC14106BD MC14106BDG MC14106BDR2 MC14106BDR2G MC14106BDTR2 MC14106BDTR2G Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* 2500 / Tape & Reel 55 Units / Rail 25 Units / Rail Shipping For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 2 II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I II I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I III II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIII I III II IIII I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII III I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII II IIII I III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I I II IIII III I I I I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIII III IIIII I I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I I I I III II III II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Total Supply Current (Note 3, 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Quiescent Current (Per Package) Input Capacitance (Vin = 0) Input Current Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) Threshold Voltage Positive-Going Hysteresis Voltage Output Voltage Vin = VDD (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Negative-Going Vin = 0 Characteristic "0" Level "1" Level Source Sink Symbol VH (5) VOH VOL VT+ VT- IOH IDD IOL Cin Iin IT VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 15 - - 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 0.9 2.5 4.0 2.2 4.6 6.8 0.3 1.2 1.6 2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001. 5. VH = VT+ - VT- (But maximum variation of VH is specified as less that VT+ max - VT- min). http://onsemi.com MC14106B - - - - - - - - - 55C 3 0.25 0.5 1.0 0.1 3.6 7.1 10.8 0.05 0.05 0.05 Max 2.8 5.2 7.4 2.0 3.4 5.0 - - - - - - - - - - - - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min 0.9 2.5 4.0 2.2 4.6 6.8 0.3 1.2 1.6 IT = (1.8 mA/kHz) f + IDD IT = (3.6 mA/kHz) f + IDD IT = (5.4 mA/kHz) f + IDD - - - - - - - - 0.00001 0.0005 0.0010 0.0015 Typ (2) - 4.2 - 0.88 - 2.25 - 8.8 25C 0.88 2.25 8.8 5.0 1.9 3.9 5.8 2.9 5.9 8.8 1.1 1.7 2.1 5.0 10 15 0 0 0 - - - - - - - - - - 3.6 7.1 10.8 0.25 0.5 1.0 0.1 0.05 0.05 0.05 Max 7.5 2.8 5.2 7.4 2.0 3.4 5.0 - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 0.9 2.5 4.0 2.2 4.6 6.8 0.3 1.2 1.6 - - - - - - - - 125C 3.6 7.1 10.8 1.0 0.05 0.05 0.05 Max 7.5 15 30 2.8 5.2 7.4 2.0 3.4 5.0 - - - - - - - - - - - mAdc mAdc mAdc mAdc mAdc Unit Vdc Vdc Vdc Vdc Vdc pF MC14106B Vout , OUTPUT VOLTAGE (Vdc) III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I IIIII I IIIII I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIII IIII IIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25C) Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 Min - - - - - - - - - Typ (6) 100 50 40 100 50 40 125 50 40 Max 200 100 80 200 100 80 250 100 80 Unit ns Output Rise Time Output Fall Time tTHL ns Propagation Delay Time tPLH, tPHL ns 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. PULSE GENERATOR VDD 14 OUTPUT INPUT 7 VSS CL tPHL OUTPUT tf 90% 50% 10% tr 20 ns INPUT 90% 50% 10% tPLH 20 ns VDD VSS VOH VOL Figure 1. Switching Time Test Circuit and Waveforms VDD 0 0 VT- VH Vin, INPUT VOLTAGE (Vdc) VT+ VDD Figure 2. Typical Transfer Characteristics http://onsemi.com 4 MC14106B APPLICATIONS Vin VH VDD VH Vout VDD Vin VSS VDD Vin VSS VDD Vout VSS Vout VSS (a) Schmitt Triggers will square up inputs with slow rise and fall times. Figure 3. VDD (b) A Schmitt trigger offers maximum noise immunity in gate applications. VDD R tw Rs Vout C R tw = RC IN Rs Vout VDD VT+ C tw Useful as Pushbutton/Keyboard Debounce Circuit. Figure 4. Monostable Multivibrator http://onsemi.com 5 MC14106B t1+t2 R t2 t1 Vin R A C VDD Vin VT+ VSS VDD VT+ VSS VT) VT- VDD Vout VT+ VSS Useful in discriminating against short pulse durations. Vout C * t1 [ RC ln VT ) VT - VDD - VT - * t2 [ RC ln VDD - VT) 1 [ RC ln f VDD - VT - VDD - VT) A *t1 + t2 & tPHL + tPLH Figure 5. Astable Multivibrator Figure 6. Integrator Vin C Vin R +EDGE -EDGE -EDGE +EDGE VDD tw VDD tw = RC ln VT+ Useful as an edge detector circuit. Vin C C C R R R Figure 7. Differentiator Figure 8. Positive Edge Time Delay Circuit http://onsemi.com 6 MC14106B PACKAGE DIMENSIONS PDIP-14 CASE 646-06 ISSUE P 14 8 B 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01 A F N -T- SEATING PLANE L C H G D 14 PL K M J M DIM A B C D F G H J K L M N 0.13 (0.005) http://onsemi.com 7 MC14106B PACKAGE DIMENSIONS SOIC-14 CASE 751A-03 ISSUE H -A- 14 8 -B- P 7 PL 0.25 (0.010) M B M 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C -T- SEATING PLANE R X 45 _ F D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SOLDERING FOOTPRINT* 7X 7.04 1 0.58 14X 14X 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MC14106B PACKAGE DIMENSIONS TSSOP-14 CASE 948G-01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V N S 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K 0.15 (0.006) T U S J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.36 14X 14X 1.26 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 CCC EEE CCC EEE CCC A -V- K1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ 0.65 PITCH DIMENSIONS: MILLIMETERS MC14106B ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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